The present invention relates to a sampling rate converter, and is suitably applied to the case where a sampling frequency of component digital video signals based on the D-1(625/50) format is converted to a sampling frequency corresponding to composite digital video signals based on the D-2 format, for example.
Heretofore, a commonly employed sampling rate converter was comprised of a digital filter for converting digital signals, which are obtained by sampling analog signals at a predetermined frequency, to an arbitrary sampling frequency.
Such a sampling rate converter was constituted by a high order oversampling filter to strictly observe the Nyquist frequency as a conversion characteristic of the transmission system.
In FIGS. 1A-1D, there is roughly illustrated an operation of a sampling rate converter constructed by an oversampling filter. In such an oversampling filter, input digital signals (indicated by character .smallcircle. in FIG. 1A) are inputted to the oversampling filter, the input digital signals being provided by sampling analog signals S.sub.VT as shown in FIG. 1A at a first sampling frequency f.sub.1 (FIG. 1B).
Subsequently, the oversampling filter oversamples input digital signals at a frequency f.sub.11 11 times larger than the frequency f.sub.1, as shown in FIG. 1C as well as resampling them at a second sampling frequency f.sub.2 (FIG. 1D) to obtain output digital signals which have values indicated by characters .quadrature. in FIG. 1A and are rate converted into frequency f.sub.2.
When a sampling frequency of component digital video signals based on the D-1 (625/50), format in a digital video tape recorder (DVTR) is converted into a sampling frequency corresponding to PAL composite digital video signals based on the D-2 (PAL) format, it is not practically possible to directly convert the sampling frequency between digital video signals since the sampling frequency must be converted from a frequency of 13.5 MHz to a frequency of 17.734475 MHz. By reason of the foregoing, it would be necessary to build an oversampling filter having approximately a length of an order of about 16,500.
Also in the converse case where a sampling frequency of PAL composite digital video signals is converted into a sampling frequency corresponding to 625/50 component digital video signals, it would be necessary to build an oversampling filter in the same circuit scale as the above described case since the sampling frequency is rate converted from a frequency of 17.734475 MHz to a frequency of 13.5 MHz. It is thus inevitable that the overall circuit scale becomes complicated and large.
To solve such a problem, a sampling rate converter has been proposed in which an oversampling filter reducing the circuit scale is built as follows. On the basis of the relationship of the sampling frequencies of 13.5 MHz and 17.734475 MHz for 625/50 component digital video signals and
composite digital video signals, an oversampling frequency is set, and then, changeable filter coefficients are input to multipliers, thus resulting in a magnification of the oversampling for weighting the sampling data.
FIG. 2 illustrates a basic construction of a sampling rate converter 1 having changeable coefficients. In the case where in a sampling rate converter 1 as shown in FIG. 2, a sampling frequency corresponding to 625/50 component digital video signals is converted into a sampling frequency corresponding to PAL composite digital video signals, for example, 625/50 component digital video signals S.sub.IND1 and output clock pulse signals CK.sub.D1 corresponding to the sampling frequency thereof are supplied as input to the timing adjusting circuit 2.
This timing adjusting circuit 2 causes data of the 625/50 component digital video signals S.sub.IND1 which were input at the rate of the clock pulse signals CK.sub.D1 to be output at the timing of the rate of the clock pulse signals CK.sub.D2 so as to convert the clock pulse frequency as well as control the timing of the data transference described below.
In addition to this, frame pulses P.sub.FD1 corresponding to one frame of the 625/50 component digital video signals S.sub.IND1 are supplied as input to reset terminals of a phase locked loop (PLL) circuit 3 and a counter 4.
The output of the PLL circuit 3 is fed back through a frequency divider 5 with a dividing ratio (=1/709379) corresponding to the number of samples of one frame (=709,379) of PAL composite digital video signals.
This enables the PLL circuit 3 to correctly synchronize with frame pulses P.sub.FD1 of the 625/50 component digital video signals, and the PLL circuit 3 generates output clock pulse signals CK.sub.D2 corresponding to the sampling frequency of the PAL composite digital video signals and supplies them to a count input terminal of a counter 4, the timing adjusting circuit 2 and an oversampling filter 6.
The counter 4 is reset by the frame pulses P.sub.FD1, and counts the output clock pulse signals CK.sub.D2, received from the PLL circuit 3, for each frame. Consequently, count data D.sub.CNT which ranges in value from zero to 709,378 is sequentially sent to a coefficient address control circuit 7.
The coefficient address control circuit 7 generates coefficient address data D.sub.COE according to the count data D.sub.CNT to read coefficients C.sub.OEFA, C.sub.OEFB, . . . from coefficient generating circuits 9A, 9B, . . . which are implemented as ROM devices (read only memories), the coefficients C.sub.OEFA, C.sub.OEFB, . . . being fed to multipliers 8A, 8B, . . . which are weighting means of the oversampling filter 6, part of which is illustrated in FIG. 3.
The relationship between coefficients C.sub.OEFA, C.sub.OEFB, . . . supplied to the multipliers 8A, 8B, . . . and the coefficient address data D.sub.COE is illustrated schematically in FIG. 4. In FIG. 4, a longitudinal axis represents the coefficient C.sub.OEF and lateral axis represents the coefficient address data D.sub.COE. The lateral axis may also be seen as a time axis. "N" is the order of the oversampling filter and is derived from the characteristic of the oversampling filter required. An impulse response characteristic of the oversampling filter is formed by N groups of the coefficient C.sub.OEF. It is to be appreciated that the impulse response characteristic is only schematically illustrated in FIG. 4.
"M" represents the numbers of the divisions between sampling points of the input signal S.sub.IND1, that is, the resolution capability, by which the oversampling frequency is decided. The coefficients are divided into groups of M, so as to store them in the coefficient generating circuits 9A, 9B, . . . the number of which are N/M. The coefficient address data D.sub.COE is generated at the rate of the clock pulse signals CK.sub.D2 in the coefficient address control circuit so that the appropriate coefficients C.sub.OEF stored in circuits 9A, 9B, . . . are read out.
The relationship between the count data D.sub.CNT and the address to be supplied to the coefficient generating circuits 9A, 9B, . . . containing the coefficient address data D.sub.COE is illustrated in FIG. 5. In the case illustrated in FIG. 5, the oversampling filter is constructed with orders N=4554, M=506. The coefficients which form the impulse response characteristic of the oversampling filter are stored in sequence at the addresses from a.sub.0, b.sub.0, . . . i.sub.0 to a.sub.505, b.sub.505, . . . i.sub.505. In the lower portion of FIG. 5, the coefficient addresses D.sub.COE which are generated at the time of each value of the count data D.sub.CNT are illustrated. In FIG. 5, with the count data D.sub.CNT sequenced through the values n, n+1, n+2, . . . at the rate of the clock pulse signals CK.sub.D2, the coefficient address data D.sub.COE is generated so that the addresses occur in the sequence [a.sub.0, b.sub.0, c.sub.0, . . .], [a.sub.386, b.sub.386, c.sub.386, . . . ], [a.sub.266, b.sub.266, c.sub.266, . . .], . . . .
The generation of the address in the coefficient generation circuit is performed on the basis of the relationship between the sampling period of the 625/50 component digital video signal and the sampling period of the
composite digital video signal so as to shift by 386 addresses cyclicly among addresses 0-505 as results from the following equation. ##EQU1##
The coefficients C.sub.OEFA -C.sub.OEFI generated in the coefficient generating circuits 9A-9I are multiplied by the output data in the multiplier. However, when the count data D.sub.CNT reaches certain predetermined values, for instance D.sub.CNT becoming D.sub.CNT =n+1 in FIG. 5, it is necessary to multiply the coefficients corresponding to D.sub.CNT=n+ 1 by the same data as the flip-flop output data which was multiplied at the time when D.sub.CNT was=n. In this case, the coefficient address control circuit 7 generates a shift control signal D.sub.SFT to stop the data transference in the flip-flop circuits 10A-10I (this data transference normally being to shift one block of data) so as to allow the multiplier to use the same flip-flop output data.
The shift control signal D.sub.SFT also is provided to the timing adjusting circuit 2. This results in temporarily stopping the conversion of the clock along with the stopping of the operation of the data transference from the flip-flop circuits 10A-10I, whereas the conversion of the clock pulse frequency would otherwise continue in the timing adjusting circuit 2.
As described above, the timing adjusting circuit 2 adjusts the timing of the 625/50 component digital video signals S.sub.IND1 input as sent to the oversampling filter 6 according to the output clock pulse signals CK.sub.D1, the output clock pulse signals CK.sub.D2, and the shift control data D.sub.SFT.
The oversampling filter 6 performs oversampling by multiplying the 625/50 component digital video signals S.sub.IND1 thus received by coefficients C.sub.OEFA, C.sub.OEFB, . . . according to the shift control data D.sub.SFT and the coefficient address data D.sub.COE, and provides its output according to output clock pulse signals CK.sub.D2. In this manner, output digital video signals S.sub.OUTD2 are obtained by converting the sampling frequency of 625/50 component digital video signals to a sampling frequency of PAL composite digital video signals.
It is to be noted that in the oversampling filter 6, input digital signals S.sub.IN are fed to a series of circuit flip-flops 10A, 10B, . . . each having a delay resulting from the output clock pulse signals CK.sub.D2. Delayed digital signals sent out from each of the flip-flops 10A, 10B, . . . are input to subsequent flip-flops 10B, . . . and to corresponding multipliers 8A, 8B, . . . .
Predetermined coefficients C.sub.OEFA, C.sub.OEFB, . . . as described above are input from the coefficient generating circuits 9A, 9B, . . . to their respective multipliers 8A, 8B, . . . , and consequently, the delayed digital signals are multiplied by the respective coefficients C.sub.OEFA, C.sub.OEFB, . . . .
Results of the multiplication are then input to each of the adders 11A, 11B, . . . for providing a total, and the result of this addition is sent out as output digital video signals S.sub.OUT.
The sampling rate converter 1 with such a construction results in a large scale circuit configuration in which the counter 4 counts values from 0 to 709378. Also, the coefficient address control circuit 7 inevitably has a large scale circuit configuration for processing the count data D.sub.CNT from the counter 4. Consequently, there is a problem in that the sampling rate converter 1 becomes large.